There has been an increasing demand for semiconductor devices with higher packing densities that are smaller and more precisely formed. Achieving these objectives continues to drive the semiconductor manufacturing industry to improve every aspect of the fabrication process. While there are numerous steps involved with fabricating semiconductors, the steps can be broken down into two major processes. The first major process is the front end of line (FEOL) process which begins with a starting wafer up to the first-metal cut. The second major process is the back end of line (BEOL) process which has been defined as all process steps after the first-metal cut.
Due to high-volume processing of semiconductors and the increased demands of high device reliability and performance, structural defects as well as other undesirable attributes must be constantly monitored and fabrication parameters modified to mitigate the undesirable attributes. Real-time testing and analysis as well as production line control is highly advantageous to prevent scrapping large volumes of production wafers.
During semiconductor fabrication, undesirable structural defects in the dielectric layers, such as line edge roughness (LER) may occur. LER refers to the variations in the sidewalls of features and may originate from LER in a patterned photoresist. LER in photoresists can be caused by various factors such as LER on chrome patterns residing on the reticle, image contrast in a system for generating the photoresist pattern, a plasma etch process which can be used to pattern the photoresist, natural properties and/or weaknesses of the photoresist materials, and the photoresist processing method. In addition, LER appearing in fabricated structures can occur as a result of damage to the patterned photoresist during an etch process.
LER present in the metal lines of the device could negatively impact the BEOL reliability of the device through various factors. First, the effective spacing of the metal lines may be reduced, resulting in an increase in the electrical field for a given voltage difference between the lines. The sharp corners caused by LER may result in a higher local electric field which could be more than two times the nominal field. In addition, LER may increase the total surface area between the lines, increasing the probability of, for example, Cu (copper) diffusion between the lines.
Such wafer defects have prompted wafer fabrication facilities to initiate wide-spread process controls in an attempt to mitigate wafer defects and increase wafer throughput. Currently, wafer fabrication facilities monitor thousands of wafer parameters in order to achieve the above-mentioned goals. Accordingly, control protocols, such as wafer level reliability (WLR) testing, continue to gain popularity as process controls for identifying potential factors that can detrimentally affect device reliability. However, there remains a need in the art for systems and methods that improve efficiency and speed in wafer fabrication while predicting the impact defects may have on device reliability and performance via real-time testing and analysis. There is also an unmet need to communicate, via a feedback method, the wafer reliability information to a fabrication facility and provide for timely and effective parameter adjustments during the fabrication process.